MOS capacitor: accumulation, depletion, inversion, and how fast

p-type silicon under 5 nm of oxide and a metal gate: its capacitance at the frequency you choose, against the ideal low- and high-frequency C–V curves, and the bands bending at the surface, from accumulation through depletion to inversion. Slow enough, the inversion layer's electrons follow the gate and the capacitance climbs back toward C_ox; faster, they can't arrive in time, and it stays low. How fast they arrive is set by generation in the silicon (its minority lifetime). (More about the model below.)

gate V frequency lifetime doping

About this simulation

The gate voltage sets the gate metal's Fermi level, and the silicon's bands bend at the surface to meet it. The band diagram is the familiar one, electron energy up: the band edges E_c and E_v (thin) and the quasi-Fermi levels E_Fn and E_Fp (thick), one Fermi level wherever the carriers are in equilibrium with each other. A slope in a quasi-Fermi level is what drives its carriers' current. Underneath, driftlet works in electrochemical potentials: electrons are a species of charge −1 with μ̄_e⁻ = E_Fn per particle, holes one of +1 with μ̄_h⁺ = −E_Fp, which is exactly the usual drift–diffusion (van Roosbroeck) model, and generation and recombination are the reaction e⁻ + h⁺ ⇌ 0. (The same lines in volts and turned over are species voltages, which earn their place where ions share the diagram, as in the electrochemistry and perovskite demos.) Negative bias pulls holes to the surface (accumulation), moderate positive bias pushes them away (depletion), and beyond threshold electrons gather in a thin inversion layer. Those electrons have to come from the silicon itself: generated thermally in the depletion region (the reaction e⁻ + h⁺ ⇌ 0 run backwards, at the Shockley–Read–Hall rate set by the lifetime τ), or diffusing in from the back contact through a bulk that holds only ~10³ of them per cm³. Either way it's slow, which is the point of the frequency control. (In a transistor, source and drain supply them at once; this is the capacitor alone.)

The electrostatic potential is drawn too, as −qφ (dotted), in the silicon and across the oxide, to show what it is and what it isn't. In the oxide, which holds no mobile charge, it's the only line there is, and its slope is the oxide field. In the silicon the band edges ride on it, E_c = −qφ + const, so it bends with them. But where it sits is a convention. This page anchors it 0.3 eV above the silicon's conduction band edge and steps it up 0.3 eV into the oxide, numbers picked arbitrarily to show that they change nothing (they're no claim about real Si/SiO₂); the library's own data would put it on the band edge, with no step, and textbooks tie it to the intrinsic level or the vacuum level, choices of the same kind. Any choice gives the same physics, once the gate's zeroCharge (the gate's Fermi level minus φ beside it, when the gate is uncharged) changes to match: the capacitance comes out the same to every digit. And φ doesn't meet the gate's Fermi level: a metal has no φ worth comparing, so the line just stops.

The capacitance is the small-signal response to a sinusoid on the gate at the chosen frequency (driftlet's impedance, C = −1/(ωZ″)), at each gate voltage, solved for every half decade and interpolated between. Slow enough, it follows the ideal low-frequency C–V curve (dashed: the oxide in series with the silicon's dQ/dψ, from the closed-form surface charge), to 5 × 10⁻⁴ of C_ox at the slowest: accumulation near C_ox, a depletion dip, and inversion back up, as the inversion layer's electrons come and go with the gate. Fast, only the holes and the depletion edge respond, and in inversion the capacitance stays at its minimum: the high-frequency curve. Its ideal form (dotted) freezes the minority charge in place; here the electrons can't be replaced at that speed but can still shift within the layer, which raises the capacitance a few percent above that ideal (a correction Brews worked out). The lower chart is the capacitance against frequency at the gate voltage you're at: in inversion, a step from one curve to the other, at the frequency where generation can just keep the layer filled. Shorter lifetimes move it up, about tenfold per decade of τ; with no generation at all (the slider's top end), the electrons can only diffuse in from the back contact, and it falls to a millihertz.

The third chart says where the silicon answers the gate's AC charge: the in-phase part of −F(δp − δn), gathered from the oxide inward (on a log scale of depth) and divided by C_oxδV, so that deep in the bulk it reaches the capacitance itself. In inversion at low frequency the electrons take it all within a few nanometres of the surface; at high frequency the holes take it at the depletion edge, ~100 nm down, while the electrons only shuffle within the layer, in and out again, which is that few percent above the frozen ideal. In between, both, and a quadrature part (not drawn) that is the loss as generation drags behind the gate. The step's frequency also depends on the gate voltage: just past threshold the inversion layer is thin and takes little charge per volt, so generation keeps it filled at a few tenths of a hertz (τ = 1 µs), ten times faster than in strong inversion. That's why, around 0.05 Hz, the C–V curve rises a little just past threshold before settling to the high-frequency one.

Flat band is at the work-function difference between gate and silicon, V_FB = −0.90 V at 10¹⁷ cm⁻³ (with silicon's electron affinity, 4.05 eV, a gate of work function near 4.15 eV, about aluminium's), whatever the anchoring of φ: the gate's zeroCharge, the step into the oxide and φ in the bulk each depend on it, but their sum, V_FB, doesn't. Threshold is where the surface has inverted as strongly as the bulk is doped, ψ_s = 2φ_F. More doping widens the window between them and deepens the dip.

It's an ideal capacitor, and classical: no fixed charge in the oxide and no traps at its interface (which shift and stretch real C–V curves), no quantum confinement of the carriers at the surface (at an oxide this thin, it takes several percent off the capacitance in accumulation and strong inversion), and no inversion layer beyond the gate's edge to feed it electrons from the side.